EDN

How SystemVerilog aids design and synthesis

The SystemVerilog extensions to Verilog 2001 have been getting a lot of attention lately, especially the new features designed to support verification and testbench design. But SystemVerilog also ...
EDN

How to improve FPGA-based ASIC prototyping with SystemVerilog

ASICs provide a solution for capturing high performance complex design concepts and preventing competitors from simply implementing comparable designs. However, creating an ASIC is a high-investment ...
Design-Reuse

Silicon Interfaces announces the release of its Open Verification Methodology (OVM) Based Gigabit Ethernet MAC SystemVerilog OVC

CAMPBELL, Calif., October 16, 2008-- Silicon Interfaces, a high-end design services and leading provider for IPs in Europe, North America and Asia-Pacific, announces the availability of their Gigabit ...
Design-Reuse

Silicon Interfaces announces the release of its Verification Methodology Manual (VMM) based USB 2.0 SystemVerilog Verification IP

CAMPBELL, Calif. -- November 3, 2008--Silicon Interfaces, a high-end design services and leading provider for IPs in Europe, North America and Asia-Pacific, under their IP Development Program - ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog?

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...