SANTA CRUZ, Calif. — There was no disagreement about the need for better quality designs at a Design and Verification Conference (DVCon) panel here Wednesday (Feb. 16). But panelists debated the ...

Groundbreaking benefits of using artificial intelligence in design verification. How SHAPley values can help engineers optimize debugging in design verification. Achieving low-latency SoC ...

Layout vs. schematic (LVS) circuit verification is an essential stage in the integrated circuit (IC) design verification cycle. However, given today’s large design sizes, numerous hierarchies, and ...

The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project ...

It’s no secret that hardware is the new currency in the chip world. It’s no longer the case that the semiconductor industry is in the hands of traditional semiconductor giants; an increasing number of ...

Cadence Design Systems has launched a data platform that pulls in the masses of data being collected by EDA tools, and is using this to enable a suite of AI-driven verification applications that aim ...