Semiconductor Engineering

Smarter Write Barriers For Arm64 In .NET CoreCLR

Introducing multiple Arm64 variants of the JIT_WriteBarrier function. Each variant is tuned for a GC mode. Because many parts ...
IEEE

Multi-bit magnetic memory based on domain wall motion in a vertical nanopillar with two perpendicularly magnetized pinning layers

Abstract: Magnetic memory devices based on vertical nanopillars are attractive for high-density, nonvolatile storage due to their thermal stability and scalability. However, achieving reliable ...
IEEE

DPIM: A 19.36 TOPS/W 2T1C eDRAM Transformer-in-Memory Chip with Sparsity-Aware Quantization and Heterogeneous Dense-Sparse Core

Abstract: This paper presents DPIM, the first 2T1C eDRAM Transformer-in-memory chip. Its high-density eDRAM cell supports large-capacity processing-in-memory (PIM) macros of 1.38 $\mathrm{Mb} / ...